1. Field of the Invention
The present invention relates to a semiconductor device that replaces a defective memory cell with a redundant memory cell, and a method of testing the semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-169344, filed Jul. 28, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
As the number of memory cells included in a semiconductor device increases, the possibility that defective memory cells will be formed increases in a manufacturing process. For this reason, when a defective memory cell is detected, the defective memory cell is replaced with a redundant memory cell to increase the yield of semiconductor devices. This technique is called “redundancy.” In a general replacing method, a row or column of a defective memory cell is replaced with a row or column of a redundant memory cell in units of rows or columns of memory cells.
When semiconductor devices are shipped, it is necessary to previously confirm whether or not a defective memory cell is properly replaced with a redundant memory cell. For example, Japanese Patent Laid-Open Publication No. H10-172297 and No. 2005-346902 disclose a semiconductor device that tests a replaced row or column of a redundant memory cell in a test operation mode. This technique is called a “redundancy test.”
There are a redundant memory row test and a redundant memory column test. Here, a redundant memory column test is explained. It is assumed in the redundant memory column test that a semiconductor testing device (hereinafter, “tester”) supplies a power voltage or a signal to a semiconductor device.
The inventors of the present invention found that when a redundant memory column test is performed, semiconductor devices of related art have the following problems. Hereinafter, the problems of the semiconductor devices of the related art are explained with reference to FIGS. 6 and 7.
FIG. 6 is a block diagram illustrating a semiconductor device of the related art that performs a redundancy memory column test. The semiconductor device of the related art includes a normal memory cell region 111 and a redundant memory cell region 112. The normal memory cell region 111 and the redundant memory cell region 112 are memory regions including multiple memory cells arranged in a matrix defined by rows and columns. Multiple memory cells aligned in a row are selected by a word line. A bit line, which defines a column, is selected by a Y-switch signal. A memory cell positioned at the intersection of the word line with the'bit line is connected to a local I/O line via the bit line. Thus, a memory cell is selected by a row and a column. Then, data stored in the memory cell is read out to the local I/O line in a reading operation of the semiconductor device of the related art. The data read out to the I/O line is read out to an external unit via an input/output circuit (not shown). In a wiring operation of the semiconductor device, data inputted via the input/output unit is written via the local I/O line and the bit line.
To select a row and a column, the semiconductor device of the related art includes a command decoder (not shown). The command decoder receives, from an external unit, any one of: an ACT command that orders activation of a word line; a READ command that orders a reading; a WRT command that orders a writing; a PRE command that orders deactivation of the semiconductor device; and an MRS command that orders setting of an operation mode. The command decoder decodes the received command, operates a control circuit based on the decoded command, and performs activation/deactivation of an internal circuit of the semiconductor device.
Upon power-on, the semiconductor device enters a pre-charge state in which a voltage at a predetermined connecting point of circuits (node) in a chip is charged up to a predetermined voltage. After the pre-charge ends, the semiconductor device automatically enters an idle state in which various commands are acceptable. When the semiconductor device receives, in the idle state, the MRS (mode resistor setting) command that orders the command decoder to set an operation mode, the command decoder sets to an internal mode resistor, based on a logic that is indicated by an address terminal and received with the MRS command, an operation mode of the semiconductor device, such as a test operation mode or a normal operation mode. The MRS command is simply called a mode resistor command.
While the normal operation mode is set to the mode resistor, a row address signal and the ACT command are inputted to an address buffer from an external tester. Then, the control circuit controls the address buffer to latch the row address signal, activates the row decoder, and thus selects memory cells aligned in a row indicated by the row address signal (which is hereinafter called selection control).
After the ACT command is supplied, the tester supplies, to the semiconductor device, the READ command or the WRT command together with a column address signal. A Y-address pre-decoder circuit 123, a column decoder 14, a redundancy Y-driver 142, and a Y-redundancy circuit 20A, which are shown in FIG. 6, are activated by the control circuit. The activated address buffer 12 buffers column address signals received from address terminals A0 (PAD A0) to A8 (PAD A8), and outputs the address signals YA<0> to YA<8> to the Y-address pre-decoder circuit 123.
The Y-address pre-decoder circuit 123 pre-decodes the address signals YA<0> to YA<8>, and outputs the resultant signals to the Y-address decoder 141. Based on the pre-decoded signals, the Y-address decoder 141 changes the level of any one of the Y-switch signals YSW000 to YSW511 to a high level, and turns on a Y switch corresponding to the high-level Y switch signal. Thus, the Y switch connects a bit line to the local I/O line.
Thus, when the Y-address decoder 141 is activated and receives pre-decode signals from the Y-address pre-decoder 143, the Y-address decoder 141 performs column selection control that connects, to the local I/O line, any one of memory cells that are aligned in a selected row and included in the normal memory cell region 111.
An address comparison circuit 20 includes a Y-redundancy circuit (CYRED) 20A and a nonvolatile memory circuit 20B. The nonvolatile memory circuit 20B stores information indicating positions of defective memory cells included in the normal memory cell region 111 (which information is called a redundant ROM address).
The Y-redundancy circuit 20A compares, to the redundant ROM address, an address signal YA received with the READ command or the WRT command from an external unit. If the address signal YA matches the redundant ROM address, the Y-redundancy circuit 20A outputs a redundancy Hit signal to the Y-address pre-decoder circuit (CYPD1) 123 and the redundancy Y-driver (RYSW) 142.
Although the Y-address pre-decoder 123 is activated, the Y-address pre-decoder 123 does not output the pre-decoded signals to the Y-address decoder 141 even when the redundancy Hit signal is received. Accordingly, the Y-address decoder 141 does not perform the column selection control so as not to access the defective memory cells.
On the other hand, the redundancy Y-driver 142 receives the redundancy Hit signal, outputs a redundancy Y-switch signal RYSW corresponding to the redundant ROM address, and performs a redundancy column selection control so as to access the redundant memory cell. Thus, defective memory cells in the normal memory cell region 111 are not accessed, and the redundant memory cells in the redundant memory cell region 112 are accessed by address replacement.
When the PRE command (pre-charge command) is supplied to the semiconductor device after the READ command or the WRT command is supplied, the activated circuits (the row decoder, the address buffer 12, the column decoder 14, the redundancy Y-driver 142, and the Y-redundancy circuit 20A) are deactivated by the control circuit. The above operations of the circuits shown in FIG. 6 are performed in the normal operation mode.
The semiconductor device of the related art further includes a Y-redundancy activation test circuit 176 that tests in the test operation mode whether or not a replaced defective memory cell is defective. The Y-redundancy activation test circuit 176 is controlled in the test operation mode. When the MRS command is supplied to the semiconductor device and the test operation mode is set to the mode resistor, the semiconductor device enters the test operation mode in which a memory cell included in the redundant memory cell region 112 is accessed.
Specifically, when the Y-redundancy activation test circuit 176 receives an address signal (MRS code) having the same logic as that of the address signal set to the Y-redundancy activation test circuit 176, the Y-redundancy activation test circuit 176 is activated, and outputs a test signal TREDY that is high level. When the semiconductor device receives a row address signal together with the ACT command from an external unit while the test operation mode is set to the mode resistor, the semiconductor device performs a row selection control that selects memory cells aligned in a row specified by the row address signal in a similar manner as in the normal operation mode.
Different from in the normal operation mode, however, even when the READ command or WRT command is supplied with the column address signal after the ACT command is supplied, the activated Y-address pre-decoder circuit 123 does not output pre-decoded signals since the test signal TREDY is inputted to the activated Y-address pre-decoder circuit 123. The Y-address decoder 141 does not receive pre-decoded signals, and therefore does not perform the column selection control in the normal memory cell region 111.
On the other hand, since the test signal TREDY is inputted to the semiconductor device, the Y-redundancy circuit 20A compares the address signal YA received from an external unit to the redundant ROM address. If the address signal YA matches the redundant ROM address, the Y-redundancy circuit 20A outputs a redundancy Hit signal to the redundancy Y-driver 142.
When the redundancy Y-driver 142 receives the redundancy Hit signal, the redundancy Y-driver 142 outputs a redundancy Y-switch signal RYSW corresponding to the redundant ROM address, and then performs a redundant-column selection control to access a redundant memory cell.
Thus, in the test operation mode, the semiconductor device of the related art cannot access memory cells included in the normal memory cell region 111, but can access memory cells included in the redundant memory cell region 112.
Since the semiconductor device of the related art has the above configuration, in the case of the circuit shown in FIG. 6, memory cells in the normal memory cell region 111 and memory cells in the redundant memory cell region 112, which are aligned in the same word line, cannot be sequentially tested while a word line is selected by supplying one ACT command. The reasons are explained hereinafter.
FIG. 7 is a timing chart illustrating an operation of the semiconductor device of the related art in the test operation mode. At the time t1, the semiconductor device decodes the ACT command supplied in synchronization with an external clock. Then, based on a row address supplied with the ACT command, the semiconductor device selects one word line in the normal memory cell region 111 and the redundant memory cell region 112.
After the ACT command is supplied, the semiconductor device decodes the WRT command supplied in synchronization with the external clock. Based on a column address supplied with the WRT command, the semiconductor device selects a first column region (position of which is indicated by Y=Y001) included in the normal memory cell region 111. Data supplied from an external unit is written in an accessed memory cell.
By the time t2, the semiconductor device decodes multiple WRT commands. Based on column addresses supplied with the respective WRT commands, the semiconductor device selects memory columns up to the last memory column (position of which is indicated by Y=YMAX) included in the normal memory cell region 111. Data supplied from an external unit is written in an accessed memory cell on each of the selected columns. When the semiconductor device receives the PRE command after receiving the final WRT command, the activated circuits of the semiconductor device are deactivated. Then, the semiconductor device enters the IDLE state.
Thus, since the semiconductor device is in the normal operation mode from the time t1 to the time t2, memory cells included in the normal memory cell region 111 are accessible, but memory cells included in the redundant memory cell region 112 are inaccessible.
At the time t2, the semiconductor device enters the test operation mode from the normal operation mode, and accesses memory cells included in the redundant memory cell region 112. To access memory cells included in the redundant memory cell region 112, it is necessary for the semiconductor device to enter the test operation mode. For this reason, the semiconductor device enters the test operation mode at the time t2 based on the supplied MRS command and a combination of logics of the address terminals A0 to A9 which are inputted to the mode resistor. Thus, the Y-redundancy activation test circuit 176 is activated, and outputs a test signal TREDY that is high-level.
The semiconductor device decodes an ACT command supplied after the MRS command from the tester in synchronization with the external clock. Based on a row address supplied with the ACT command, the semiconductor device selects one word line in the normal memory cell region 111 and the redundant memory cell region 112.
The semiconductor device decodes a WRT command supplied after the ACT command from the tester in synchronization with the external clock. Based on a column address supplied with the WRT command, the semiconductor device selects a first column region (position of which is indicated by Y=TY001) in the redundant memory cell region 112. Data supplied from an external unit is written in an accessed memory cell.
By the time t3, the semiconductor device decodes multiple WRT commands. Based on column addresses supplied with the respective WRT commands, the semiconductor device selects memory columns up to the last memory column (position of which is indicated by Y=TYMAX) included in the redundant memory cell region 112. Data supplied from the tester is written in an accessed memory cell in each of the selected columns. When the PRE command is received from the tester after the final WRT command, the activated circuits of the semiconductor device are deactivated. Then, the semiconductor device enters the IDLE state.
Thus, since the semiconductor device is in the test operation mode from the time t2 to the time t3, memory cells included in the redundant memory cell region 112 are accessible, but memory cells included in the normal memory cell region 111 are inaccessible.
The ACT command, the WRT command (or READ command), the PRE command, and the MRS command, which are supplied from the tester in the above test, are commands belonging to the same hierarchy (first hierarchy). The commands belonging to the same hierarchy are commands whose orders cannot be simultaneously performed by the semiconductor device. This is because the commands are supplied from the common external terminals.
Specifically, even if the mobile station device receives the MRS command while maintaining the state of the circuits activated by a supply of the ACT command, the mobile station device cannot perform the test mode operation specified by the MRS command. To perform the test mode operation, the tester has to supply, before supplying the MRS command, the PRE command to the semiconductor device so that the semiconductor device enters the idle mode.
For this reason, as explained above, a command that selects the redundant memory cell region 112 (MRS command) has to be inputted in order to sequentially access the two exclusive regions (the normal memory cell region 111 and the redundant memory cell region 112). In other words, one ACT command is inputted to activate an internal circuit. After the ACT command, the WRT command or READ command is supplied to access memory cells included in the normal memory cell region 111. Then, the PRE command is supplied to cause the semiconductor device to enter the IDLE state. To access a redundant memory cell, the MRS command is inputted to cause the semiconductor device to enter the test operation mode. In the test operation mode, the ACT command is inputted after the MRS command to activate respective internal circuits. Then, the WRT command or READ command is supplied after the ACT command to access memory cells included in the redundant memory cell region 112, in a similar manner as in the normal operation mode.
Thus, the semiconductor device of the related art sequentially tests memory cells included in the normal memory cell region 111 and memory cells included in the redundant memory cell region 112, which cannot be accessed simultaneously. For this reason, at each time of switching these regions, the tester has had to supply the ACT command, the PRE command, and the MRS command to the semiconductor device of the related art.
In other words, when an evaluation test of redundant memory cells is performed, the semiconductor device of the related art cannot access both the normal memory cell region 111 and the redundant memory cell region 112 during an operation cycle specified by one ACT command (while one word line is selected). Therefore, the semiconductor device of the related art has had to access these regions separately, thereby requiring a long testing time, and therefore causing an increase in testing cost.
Japanese Patent Laid-Open Publication No. H10-172297 discloses a semiconductor device that recognizes an address signal AX, which is received from an external unit based on a test mode signal TE, as an upper address indicating a redundant memory cell region. However, this is just technique of switching between the operation for the redundant memory cell region and the operation for the normal memory cell region by adding the upper bit AX. The adding of the upper bit AX to the address decoder, which is also used in the normal operation mode for an upper bit AX test, causes an increase in the number of gate inputs of the decoder and an increase in the number of gate stages, and thereby causes an access delay in the normal operation mode.
Japanese Patent Laid-Open Publication No. 2005-346902 only discloses a semiconductor device that uses a different operation timing for a control circuit to access a memory cell between an access to a normal memory cell and an access to a redundant memory cell when a redundant address signal corresponding to a redundant memory cell is received from a mode resistor to which a redundant address detection mode is set.